There are a number of conventional processes for packaging integrated circuit (IC) dice. By way of example, many IC packages utilize a metallic leadframe that has been stamped or etched from a metal sheet to provide electrical interconnects to external devices. The die may be electrically connected to the leadframe by means of bonding wires, solder bumps or other suitable electrical connections. In general, the die and portions of the leadframe are encapsulated with a molding material to protect the delicate electrical components on the active side of the die while leaving selected portions of the leadframe exposed to facilitate electrical connection to external devices.
The resultant IC packages are often mounted onto printed circuit boards (PCBs). The PCB is used to mechanically support and electrically connect electronic components including the IC package using conductive pathways, or traces, typically etched from copper sheets laminated onto a non-conductive substrate. In many applications, it is desirable to position various non-active (or passive) components along some of the traces to interrupt certain signal transmission paths between the die and an external device or power supply. By way of example, one or more of resistors, capacitors and/or inductors are often mounted onto the PCB. A bypass capacitor, for instance, is often used to decouple one part of the circuit from another. More specifically, a bypass capacitor may be used to bypass the power supply or other high impedance component of the circuit.
Unfortunately, the extended lengths of the signal transmission paths themselves lead to increased parasitic resistances and inductances in the circuit. By way of example, in applications utilizing leadframes with bonding wires, the path length of a given signal is roughly equal to the sum of the lengths of the bonding wire, the length of the lead, the length of the trace coupling the lead to a passive component(s), the length of the passive component(s) and the length of the trace coupling the passive component(s) to an external device. Higher resistance and increased inductance are particularly problematic in high speed applications such as high speed analog to digital converters (ADCs) in which it is desirable to maximize the operating frequency and minimize the time delay.
While existing arrangements and methods for packaging IC devices work well, there are continuing efforts to both miniaturize the size of IC devices and improve the electrical performance of IC devices.